The present invention relates to semiconductor processing, and more specifically to the fabrication of combined integrated circuits having both a dynamic random access memory (DRAM) and other circuits, wherein the DRAM includes an array of vertical transistor devices.
Significant challenges exist in the fabrication of combined integrated circuits having both an embedded DRAM and other circuit components, e.g. CMOS logic circuits. Processes which are required for high performance CMOS logic are difficult to mate with DRAM processing requirements. For example, high performance CMOS logic requires gate conductors to have narrow line widths to support higher switching speeds. Narrow line width gate conductors, smaller than lithographically printable line widths, can be made by first printing and etching photoresist patterns, and then etching the sidewalls of the patterns in what is known as xe2x80x9cmask trimxe2x80x9d prior to etching an underlying gate conductor layer. High performance CMOS logic also favors gate conductors having mostly silicide or metal content and little to no polysilicon content.
On the other hand, conventional DRAMs having planar device arrays require gate conductors to have certain characteristics which reduce off current (the current when the memory array transistor is biased below threshold voltage), in order to support the required data retention time between successive refresh cycles. First, somewhat wider line width gate conductors are required than for logic, with width at about the minimum groundrule. Second, gate conductors must be of polysilicon, rather than silicide or metal, where they contact the gate oxide. Third, gate conductor lines in planar DRAMs require sidewall oxidations.
Also, unlike CMOS logic circuits, gate conductor lines are spaced very closely, leaving about 1F space or less (the minimum groundrule) between adjacent gate conductors in planar DRAMs. Consequently, in planar DRAMs, only borderless bitline contacts can be used. Borderless bitline contacts have conductive studs which at least partially overlie the tops of adjacent gate conductors. Because of this, thick dielectric caps must be formed on top of the gate conductors, as insulators for the borderless bitline contacts which overlie them. Such thick dielectric caps increase process complexity and undesirably increase the height and aspect ratio of gaps between adjacent gate conductors which are to be filled by deposited dielectric.
It would be desirable to simplify the processing of combined integrated circuits having both a logic portion and an embedded DRAM portion, such that gate conductor lines in the logic portion can be processed together with wordlines in the DRAM array portion.
Accordingly, it would be desirable to use narrow line width wordlines in the DRAM array which are fabricated together with the narrow line width gate conductors of the logic circuitry. It would also be desirable to use a bordered, rather than borderless, bitline contact in the DRAM array, such that the dielectric capping layer over the wordline could be eliminated.
According to a first aspect of the invention, an integrated circuit including a dynamic random access memory (DRAM) array is provided in which a DRAM cell includes a storage capacitor within a deep trench, a transistor having a channel extending along a sidewall of the deep trench and a gate conductor within the deep trench, and a wordline contacting the gate conductor from above, wherein the wordline has a centerline which is offset from the centerline of the gate conductor. The DRAM cell further includes active area extending from the transistor channel, and a bitline contact to the active area which is bordered by an insulating spacer on the sidewall of the wordline.
According to another aspect of the invention, a method is provided for fabricating a dynamic random access memory array, which includes etching deep trenches in a substrate; forming storage capacitors and transistors within the deep trenches, and forming active areas extending from the deep trenches. Such method further includes forming top oxide layers above the active areas and forming wordlines contacting gate conductors of the vertical transistors from above, the wordlines contacting the top oxide layers from above, and the wordlines further having centerlines horizontally offset from centerlines of the gate conductors. Bitline contacts to the active areas are formed through apertures etched in the top oxide layers.